1. Field of the Invention
The present disclosure relates to display technology, and more particularly to an array substrate and a liquid crystal display.
2. Discussion of the Related Art
TFT-LCDs include array substrates with a plurality of pixel areas respectively corresponding to R, G, and B arranged thereon. In addition, TFT-LCDs also include scanning lines, data lines, TFT for controlling the pixel areas and storage capacitors and liquid crystal capacitors.
Currently, color shift often occurs in wide viewing angle for Vertical Alignment (VA) large-scale LCDs.
In order to overcome this problem, one general solution is to divide one pixel area to a main-area A and a sub-area B, and light beams are not able to pass through the location between the main-area A and the sub-area B. When the grayscale values of video signals are the same, the voltages applied to the two areas are different to obtain different γ curves. The difference of the visual effect of the γ curve formed by the two areas between a wide-viewing-angle-view and a narrow-viewing-angle-view is reduced, which greatly enhanced the color shift issue in wide viewing angle.
FIG. 1 is a schematic view of the charging sharing 08 (CS) circuit of the array substrate of one conventional TFT-LCD. Referring to FIG. 1, each pixel areas includes a data line 110, a first scanning line 120, a second scanning line 130, a first pixel electrode 140, a second pixel electrode 150, a first thin film transistor (TFT_A), a second thin film transistor (TFT_B), and a third thin film transistor (TFT_C). The data line 110 connects to the source of the TFT_A and the TFT_B. The first pixel electrode 140 connects to the drain of the TFT_A. The second pixel electrode 150 connects to the drain of the TFT_B. The second scanning line 130 connects to the gate of the TFT_C to provide scanning signals. The drain of the TFT_C connects to the second pixel electrode 150. The source of the TFT_C connects to the common electrode via the first capacitor (Cs1).
The TFT-LCD is driven in a row-by-row manner. When the n-th row is scanned, the signals (Vgn) of the first scanning line 120 is at a high level and the signals (Vgn+1) of the second scanning line 130 is at a low level. The TFT_A and TFT_B are turn on and the TFT_C is turn off. The data line 110 charges the first storage capacitor (Cst_A) and the first liquid crystal capacitor (Clc_A) connected with the first pixel electrode 140 and the second storage capacitor (Cst_B) and the second liquid crystal capacitor (Clc_B). The pixel voltage (VA) of the first pixel electrode 140 and the pixel voltage (VB) of the second pixel electrode 150 are charged until being equal to the voltage (Vd) of the data line 110. When the (n+1)-th row is scanned, the signals (Vgn) of the first scanning line 120 is switched to the low level, and the signals (Vgn+1) of the second scanning line 130 is switched to the high level. The TFT_A and the TFT_B are turn off, and the TFT_C is turn on. The pixel voltage (VB) of the second pixel electrode 150 discharges toward the common electrode via the first capacitor Cs1 to change the pixel voltage (VB) of the second pixel electrode 150. As such, the pixel voltage (VA) of the first pixel electrode 140 is different from the pixel voltage (VB) of the second pixel electrode 150, which achieves the low color shift (LCS) effect. Assuming that the VA and the VB respectively represents the pixel voltage of the “A area” and the “B area,” the ratio of VB to VA can be shown by the equation of:VB/VA=(Cst_B+Clc_B)/(Cst_B+Clc_B+2Cs1)
The ratio of VB/VA is a key factor, wherein the capacitor (Cs1) plays an important role of determining the value of the ratio of VB to VA.
FIG. 2 is a schematic view of the capacitor (Cs1) of FIG. 1. Referring to FIG. 2, the capacitor (Cs1) includes a first metallic layer (M1), an insulation layer (SiNx), a semiconductor layer (a-si) and a second metallic layer (M2). The first metallic layer (M1) and the second metallic layer (M2) correspond to a gate metallic layer and a source metallic layer of the array substrate. That is, the metallic gate of the TFT is formed by sputtering a gate metallic layer on the array substrate, and then the first metallic layer (M1) is formed by etching the gate metallic layer. The metallic source of the TFT is formed by sputtering a source metallic layer on the array substrate, and then the second metallic layer (M2) is formed by etching the source metallic layer. The insulation layer (SiNx) corresponds to the gate insulation layer on the array substrate. The array substrate corresponds to the TFT semiconductor layer on the array substrate. That is, the TFT semiconductor layer is formed on the array substrate, and the lithographic process is applied to form the TFT semiconductor layer. In addition, the lithographic process is applied to form the semiconductor layer (AS) of the capacitor. Generally, the second metallic layer (M2) connects to the voltage of the pixel electrode, and the first metallic layer (M1) connects to the lines of the common electrode.
FIG. 3 is a curve diagram of the capacitor-voltage (C-V) of the capacitor (Cs1). As shown, the capacitance of the positive half cycle is larger than that of the negative half cycle. The positive half cycle relates to one period during which the voltage of the pixel electrode, i.e., VB or VA, is larger than that of the Vcom, and the negative half cycle relates to one period during which the voltage of the pixel electrode is smaller than that of the Vcom. For each pixel areas, the positive half cycle and the negative half cycle are interleaved so as to drive the TFT-LCD. Preferably, the VB/VA ratios of the positive and negative half cycle remain the same. However, the capacitance of the positive half cycle is generally larger than or smaller than that of the negative half cycle such that the VB/VA ratio of the positive half cycle is smaller.
Therefore, the color shift circuit, such as CS08, may results in asymmetric positive half cycle and negative half cycle due to the different VB/VA ratios. In addition to the affected color shift effect, the color shift circuit may result in image sticking.